Archive for January, 2008

VHDL

Tuesday, January 29th, 2008

So my class for this quarter is called ‘Silicon Programming’ which is basically a grandfathered name for a class which is turning into an embedded systems/FPGA class. So far it’s required me to dig back into the shadows of memory for all of the digital systems design and computer organization stuff I haven’t used for about 6 to 7 years. It’s been fun remembering how to build adders, and how to use flip-flops to build memory and stuff like that, but it’s been a challenge.

So now that the review portion of the class is over, we’re moving on to using VHDL to build our circuit designs. Except, they’re not really ‘circuit designs’ in the traditional sense of having a schematic. (At this point, if you already know a bit about VHDL, you can probably sit back and be amused at my ignorance. Hey – I’m still learning and this is still new to me!) THe VHDL language is interesting. There are several styles of which you can describe the hardware. The styles range from describing a circuit-like implementation, to describing what the behavior of the circuit is (letting the compiler do the work of figuring out the best way to implement it.

The interesting, and pretty cool thing about VHDL is that it is inherently parallel in nature. Think about some of the circuit designs you’ve done (or seen). As a simple example: How many wires were tying a single input to multiple gates? And remember all of the latches/flip-flops that used their own output as an input. There’s lot of weird things that happen in real systems when compared to software systems. Oh sure, there’s interprocess communication that has to happen, especially when handling mutli-threaded apps. But that seems fairly trivial when trying to describe the behavioral actions of parallel circuit paths!

It’s fun, but it’s also a struggle….hopefully I figure it out!